1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device, and more particularly, to a semiconductor device having trench structures and a method of fabricating the same.
2. Description of the Prior Art
Having the advantages of a high operational bandwidth, a high operational efficiency, and a planar structure that eases the integration in other integrated circuits, lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor devices are widely used in high operational voltage environments such as CPU power supplies, power management systems, AC/DC converters, and high-power or high frequency (HF) band power amplifiers.
Please refer to FIG. 1. FIG. 1 is a cross-sectional view illustrating a LDMOS transistor device. As shown in FIG. 1, a LDMOS transistor device 10 includes a P-type substrate 11, an N-type well 12 disposed in the substrate 11, a field oxide layer 13 disposed on the substrate 11, a gate 14 disposed on a part of the field oxide layer 13, and a spacer 15 disposed beside the gate 14. A P-type doped region 16 is located in the N-type well 12. The source 17 is located in the P-type doped region 16 at one side of the spacer 15 and the drain 18 is disposed in the N-type well 12 at the other side of the spacer 15. The main characteristics of the LDMOS transistor device are the lateral diffused area having the low dopant concentration and the large area disposed in the drain region that buffers the high voltage signals between the source region and the drain region. Accordingly, LDMOS transistor devices can have a high breakdown voltage (Vbd).
With the trend of miniaturization of the electronic products, how to reduce the occupied area of LDMOS transistor device in the semiconductor substrate without adversely affecting the LDMOS transistor performance is an important issue in this field.